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MC14001UB, MC14011UB UB-Suffix Series CMOS Gates
The UB Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired. The UB set of CMOS gates are inverting non-buffered functions.
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* Supply Voltage Range = 3.0 Vdc to 18 Vdc * Linear and Oscillator Applications * Capable of Driving Two Low-power TTL Loads or One Low-power * *
Schottky TTL Load Over the Rated Temperature Range Double Diode Protection on All Inputs Pin-for-Pin Replacements for Corresponding CD4000 Series UB Suffix Devices
MC14001UB Quad 2-Input NOR Gate MC14011UB Quad 2-Input NAND Gate
MARKING DIAGRAMS
14
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 2.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value - 0.5 to +18.0 - 0.5 to VDD + 0.5 10 500 - 55 to +125 - 65 to +150 260 Unit V V
PDIP-14 P SUFFIX CASE 646
MC140XXUBCP AWLYYWW 1 14
mA mW C C C
SOIC-14 D SUFFIX CASE 751A 1
140XXU AWLYWW
1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
XX = Specific Device Code A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week
ORDERING INFORMATION
Device MC14001UBCP MC14001UBD MC14001UBDR2 MC14011UBCP MC14011UBD MC14011UBDR2 Package PDIP-14 SOIC-14 SOIC-14 PDIP-14 SOIC-14 SOIC-14 Shipping 2000/Box 55/Rail 2500/Tape & Reel 2000/Box 55/Rail 2500/Tape & Reel
v
v
(c) Semiconductor Components Industries, LLC, 2000
1
March, 2000 - Rev. 3
Publication Order Number: MC14001UB/D
MC14001UB, MC14011UB
LOGIC DIAGRAMS
MC14001UB Quad 2-Input NOR Gate 1 2 5 6 8 9 12 13 3 4 10 11 1 2 5 6 8 9 12 13 MC14011UB Quad 2-Input NAND Gate 3 4 10 11
VDD = PIN 14 VSS = PIN 7 FOR ALL DEVICES
PIN ASSIGNMENTS
MC14001UB Quad 2-Input NOR Gate
IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C
MC14011UB Quad 2-Input NAND Gate
IN 1A IN 2A OUTA OUTB IN 1B IN 2B VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD IN 2D IN 1D OUTD OUTC IN 2C IN 1C
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II I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIIII I IIII I IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I IIII I IIII I IIII I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I IIII I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I IIII I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I IIII I IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I IIII I II I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIII I IIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III III I I I I I I I I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIII II I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
3. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 4. The formulas given are for the typical characteristics only at 25_C. 5. To calculate total supply current at loads other than 50 pF:
where: IT is in H (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per package.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Total Supply Current (4.) (5.) (Dynamic plus Quiescent, Per Gate CL = 50 pF)
Quiescent Current (Per Package)
Input Capacitance (Vin = 0)
Input Current
Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)
Input Voltage (VO = 4.5 Vdc) (VO = 9.0 Vdc) (VO = 13.5 Vdc)
Output Voltage Vin = VDD or 0
(VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)
(VO = 0.5 Vdc) (VO = 1.0 Vdc) (VO = 1.5 Vdc)
Vin = 0 or VDD
Characteristic
IT(CL) = IT(50 pF) + (CL - 50) Vfk
"1" Level
"1" Level
"0" Level
"0" Level
Source
Sink
Symbol
VOH
VOL
IOH
IDD
Cin
IOL
VIL
IIH
Iin
IT
MC14001UB, MC14011UB
VDD Vdc
5.0 10 15
5.0 10 15
5.0 10 15
5.0 5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
15
--
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- 1.2 - 0.25 - 0.62 - 1.8 4.95 9.95 14.95 4.0 8.0 12.5 0.64 1.6 4.2 MinIII Max -- -- -- -- -- -- -- -- -- -- -- - 55_C 0.1 0.25 0.5 1.0 0.05 0.05 0.05 1.0 2.0 2.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4.95 9.95 14.95 - 1.0 - 0.2 - 0.5 - 1.5 IT = (0.3 A/kHz) f + IDD/N IT = (0.6 A/kHz) f + IDD/N IT = (0.8 A/kHz) f + IDD/N 4.0 8.0 12.5 0.51 1.3 3.4 Min -- -- -- -- -- -- -- -- -- -- -- 0.00001 Typ (3.) 0.0005 0.0010 0.0015 - 1.7 - 0.36 - 0.9 - 3.5 25_C 0.88 2.25 8.8 2.75 5.50 8.25 2.25 4.50 6.75 5.0 5.0 10 15 0 0 0 0.1 0.25 0.5 1.0 0.05 0.05 0.05 Max 7.5 1.0 2.0 2.5 -- -- -- -- -- -- -- -- -- -- -- -- -- - 0.7 - 0.14 - 0.35 - 1.1 4.95 9.95 14.95 4.0 8.0 12.5 0.36 0.9 2.4 Min -- -- -- -- -- -- -- -- -- -- -- 125_C 1.0 0.05 0.05 0.05 Max 7.5 15 30 1.0 2.0 2.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- mAdc mAdc Adc Adc Adc Unit Vdc Vdc Vdc Vdc pF
3
MC14001UB, MC14011UB
III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I III I I I I I IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C)
Characteristic Symbol tTLH VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 Min -- -- -- -- -- -- -- -- -- Typ (7.) 180 90 65 100 50 40 90 50 40 Max 360 180 130 200 100 80 180 100 80 Unit ns Output Rise Time tTLH = (3.0 ns/pF) CL + 30 ns tTLH = (1.5 ns/pF) CL + 15 ns tTLH = (1.1 ns/pF) CL + 10 ns Output Fall Time tTHL = (1.5 ns/pF) CL + 25 ns tTHL = (0.75 ns/pF) CL + 12.5 ns tTHL = (0.55 ns/pF) CL + 9.5 ns tTHL ns Propagation Delay Time tPLH, tPHL = (1.7 ns/pF) CL + 30 ns tPLH, tPHL = (0.66 ns/pF) CL + 22 ns tPLH, tPHL = (0.50 ns/pF) CL + 15 ns tPLH, tPHL ns 6. The formulas given are for the typical characteristics only at 25_C. 7. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 20 ns VDD 14 PULSE GENERATOR INPUT * 7 VSS tTHL OUTPUT tPHL CL OUTPUT INVERTING 90% 50% 10% tTLH INPUT 90% 50% 10% tPLH VOH VOL 20 ns VDD 0V *All unused inputs of AND, NAND gates must be connected to VDD. All unused inputs of OR, NOR gates must be connected to VSS.
Figure 1. Switching Time Test Circuit and Waveforms
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MC14001UB, MC14011UB
MC14001UB CIRCUIT SCHEMATIC
VDD 14
MC14011UB CIRCUIT SCHEMATIC (1/4 of Device Shown)
14 VDD
3
10
1
8
2
9
3, 4, 10, 11 1, 6, 8, 13 2, 5, 9, 12
6
13
7 VSS
5
12
4
7 VSS
11
16 14 Vout , OUTPUT VOLTAGE (Vdc) 12 10 8.0 6.0 4.0
Vout , OUTPUT VOLTAGE (Vdc)
I D, DRAIN CURRENT (mAdc)
VDD = 15 Vdc TA = + 25C Unused input connected to VSS. a One input only 10 Vdc b Both inputs 8.0 b 5.0 Vdc b ba a a 6.0 15 Vdc 4.0 10 Vdc 2.0 0 0 2.0 4.0 6.0 8.0 10 12 14 16 Vin, INPUT VOLTAGE (Vdc)
16 14 12 10 8.0
VDD = 15 Vdc Unused input connected to b VSS. a 10 Vdc a TA = + 125C b TA = - 55C a b
6.0 4.0 2.0 0 0
5.0 Vdc ab
2.0 0
2.0 4.0 6.0 8.0 10 12 14 16 Vin, INPUT VOLTAGE (Vdc)
Figure 2. Typical Voltage and Current Transfer Characteristics
Figure 3. Typical Voltage Transfer Characteristics versus Temperature
0 VGS = - 5.0 Vdc a TA = - 55C b TA = + 25C c TA = + 125C c - 10 Vdc - 8.0 b
c b a I D, DRAIN CURRENT (mAdc)
10 a 8.0 b c a b c a TA = - 55C b TA = + 25C c TA = + 125C a b c 5.0 Vdc VGS = 10 Vdc 15 Vdc
I D, DRAIN CURRENT (mAdc)
- 2.0
- 4.0
6.0
- 6.0
4.0
c
b a a - 2.0
- 15 Vdc
2.0
- 10 - 10
0 0 0 2.0 4.0 6.0 VDS, DRAIN VOLTAGE (Vdc) 8.0 10
- 8.0
- 6.0 - 4.0 VDS, DRAIN VOLTAGE (Vdc)
Figure 4. Typical Output Source Characteristics
Figure 5. Typical Output Sink Characteristics
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MC14001UB, MC14011UB
PACKAGE DIMENSIONS
P SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE M
14 8
B
1 7
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10_ 0.38 1.01
A F N -T-
SEATING PLANE
L C
K H G D 14 PL 0.13 (0.005)
M
J M
DIM A B C D F G H J K L M N
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MC14001UB, MC14011UB
PACKAGE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
M
K TB
S
M A
S
J
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
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MC14001UB, MC14011UB
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MC14001UB/D

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